Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation. (arXiv:2303.07445v1 [cs.AR])
DRAM is the primary technology used for main memory in modern systems.
Unfortunately, as DRAM scales down to smaller technology nodes, it faces key
challenges in both data integrity and latency, which strongly affect overall
system reliability, security, and performance. To develop reliable, secure, and
high-performance DRAM-based main memory for future systems, it is critical to
rigorously characterize, analyze, and understand various aspects (e.g.,
reliability, retention, latency, RowHammer vulnerability) of existing DRAM
chips and their architecture. The goal of this dissertation is to 1) develop
techniques and infrastructures to enable such rigorous characterization,
analysis, and understanding, and 2) enable new mechanisms to improve DRAM
performance, reliability, and security based on the developed understanding.
To this end, in this dissertation, we 1) design, implement, and prototype a
new practical-to-use and flexible FPGA-based DRAM characterization
infrastructure (called SoftMC), 2) use the DRAM characterization infrastructure
to develop a new experimental methodology (called U-TRR) to uncover the
operation of existing proprietary in-DRAM RowHammer protection mechanisms and
craft new RowHammer access patterns to efficiently circumvent these RowHammer
protection mechanisms, 3) propose a new DRAM architecture, called SelfManaging
DRAM, for enabling autonomous and efficient in-DRAM maintenance operations that
enable not only better performance, efficiency, and reliability but also faster
and easier adoption of changes to DRAM chips, and 4) propose a versatile DRAM
substrate, called the Copy-Row (CROW) substrate, that enables new mechanisms
for improving DRAM performance, energy consumption, and reliability.