Libre-SOC’s Open Hardware 180nm ASIC Submitted To IMEC for Fabrication
“We’re building a chip. A fast chip. A safe chip. A trusted chip,” explains the web page at “A chip with lots of peripherals. And it’s VPU. And it’s a 3D GPU… Oh and here, have the source code.”

And now there’s big news, reports long-time Slashdot reader lkcl:

Libre-SOC’s entirely Libre 180nm ASIC, which can be replicated down to symbolic level GDS-II with no NDAs of any kind, has been submitted to IMEC for fabrication.

It is the first wholly-independent Power ISA ASIC outside of IBM to go Silicon in 12 years. Microwatt went to Skywater 130nm in March; however, it is also developed by IBM, as an exceptionally well-made Reference Design, which Libre-SOC used for verification.

Whilst it would seem that Libre-SOC is jumping on the chip-shortage era’s innovation bandwagon, Libre-SOC has actually been in development for over three and a half years so far. It even pre-dates the OpenLane initiative, and has the same objectives: fully automated HDL to GDS-II, full transparency and auditability with Libre VLSI tools Coriolis2 and Libre Cell Libraries from Chips4Makers.

With €400,000 in funding from the NLNet Foundation [a long-standing non-profit supporting privacy, security, and the “open internet”], plus an application to NGI Pointer under consideration, the next steps are to continue development of Draft Cray-style Vectors (SVP64) to the already supercomputer-level Power ISA, under the watchful eye of the upcoming OpenPOWER ISA Workgroup.

Read more of this story at Slashdot.

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Author Of this post: EditorDavid

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