This letter presents an energy- and memory-efficient pattern-matching engine
for a network intrusion detection system (NIDS) in the Internet of Things.
Tightly coupled architecture and circuit co-designs are proposed to fully
exploit the statistical behaviors of NIDS pattern matching. The proposed engine
performs pattern matching in three phases, where the phase-1 prefix matching
employs reconfigurable pipelined automata processing to minimize memory
footprint without loss of throughput and efficiency. The processing elements
utilize 8-T content-addressable memory (CAM) cells for dual-port search by
leveraging proposed fixed-1s encoding. A 65-nm prototype demonstrates
best-in-class 1.54-fJ energy per search per pattern byte and 0.9-byte memory
usage per pattern byte.
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Author Of this post: <a href="http://arxiv.org/find/cs/1/au:+Li_D/0/1/0/all/0/1">Dai Li</a>, <a href="http://arxiv.org/find/cs/1/au:+Yang_K/0/1/0/all/0/1">Kaiyuan Yang</a>